Fujitsu FR81S User Manual
CHAPTER 46: WORKFLASH MEMORY
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WORKFLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.2. WorkFlash Status Register : DFSTR (WorkFlash
STatus Register)
The bit configuration of the WorkFlash status register is shown below.
This register indicates the WorkFlash status.
DFSTR: Address 2303
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
DFECCERR
DFHANG DFRDY
Initial value
-
-
-
-
-
0
0
1
Attribute RX,WX
RX,WX
RX,WX
RX,WX
RX,WX
R/W
R,WX
R,WX
[bit7 to bit3] Reserved
These bits are reserved. The read value is undefined. Writing has no effect on the operation.
[bit2] DFECCERR (WorkFlash ECC Error coRRection) : data read ECC correction occurred
This bit indicates that ECC error occurs when reading data of WorkFlash in the CPU mode. This bit is
cleared by writing "0". Writing "0" is prioritized when ECC error and writing "0" occur concurrently.
DFECCERR
Read
Write
0
An error correction by ECC has not occurred during data read
(initial value)
Clears this bit
1
ECC error correction occurred during data read
No effect
If there are errors in 2-bit or more in a single word, the read value of this bit is undefined.
[bit1] DFHANG (WorkFlash HANG) : WorkFlash HANG status
This bit indicates the WorkFlash memory HANG status. If there is a timing overrun (See "[bit5]: TLOV:
(Timing Limit Elapsed Flag Bit) "), the flash memory will go into the HANG status. If this bit becomes "1",
issue the Reset command (See "5.3.1 Command Sequence").
The correct value might not be read out immediately after a command of automatic algorithm has been
issued. Therefore, ignore the first read value of this bit after the command issuance.
DFHANG
Description
0
Normal state
1
HANGUP state
MB91520 Series
MN705-00010-1v0-E
1981