Fujitsu FR81S User Manual
CHAPTER 46: WORKFLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WORKFLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
Figure 5-2 Example of Write Procedure
Notes:
⋅
If write completes, the write address is not accepted because the flash memory returns to the read mode.
⋅
See "5.3 Automatic Algorithm" for details on the write command.
⋅
Because the value of the DPOLL bit of the hardware sequence flag changes concurrently with the TLOV
bit, check this bit again even if the value of the TLOV bit is "1".
⋅
The moment when the TOGG1 bit of the hardware sequence flag and TLOV bit change to "1", the toggle
operation stops. Therefore, even if the TLOV bit is "1", checking the TOGG1 bit again must be needed.
⋅
Although the flash memory can be written to in any order of addresses, even if it crosses a sector
boundary, only a single half-word data can be written in each write command sequence. If you want to
write multiple data, issue one write command sequence for each data.
⋅
Data that has been written to "0" once cannot be returned to "1". If "0" is rewritten with "1", one of the
following occurs.
-The element is judged as faulty by the data polling algorithm.
-The write rated time is exceeded, and the TLOV bit of the hardware sequence flag
changes to "1".
No
Yes
0
1
Start of writing
Set the FWE bit of work flash control
register (DFCTLR) to enable writing
to flash (FWE = 1).
Write command sequence
(1) Addr: AA8 Data: 00AA
(2) Addr: 554 Data: 0055
(3) Addr: AA8 Data: 00A0
(4) Addr: Address Data: Data
Internal address reading out
Next address
Data
Reading out (dummy)
*
Data polling
(DPOLL bit)
Inverted data
Timing limit
(TLOV bit)
Write error
Last address
Set the FWE bit of work flash control
register (DFCTLR) to disable writing
to flash (FWE = 0).
End of writing
: Verify with a hardware sequence flag.
*: When reading out the
DFSTR register instead of
reading out the hardware
sequence flag, ignore the
first read value (it is
unnecessary to read out the
dummy when reading out
the hardware sequence
Set the FEW bit of the WorkFlash
control register (DFCTLR) to
disable writing to flash (FEW = 0)
Set the FEW bit of the WorkFlash
control register (DFCTLR) to enable
writing to flash (FEW = 1)
flag.)
MB91520 Series
MN705-00010-1v0-E
2000