Fujitsu FR81S User Manual
CHAPTER 47: ON CHIP DEBUGER (OCD)
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: ON CHIP DEBUGGER : OCD
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
3.1.2. DEBUG I/F PLL Clock : M_PCLK
DEBUG I/F PLL clock (M_PCLK) is shown.
When the OCD tool is connected and the high-speed UART mode or phase modulation UART mode is
selected, the PLL clock (PLLCLK) is supplied for DEBUG I/F PLL clock (M_PCLK).
When the OCD tool is not connected, DEBUG I/F PLL clock (M_PCLK) stops.
MB91520 Series
MN705-00010-1v0-E
2020