Fujitsu FR81S User Manual
CHAPTER 47: ON CHIP DEBUGER (OCD)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: ON CHIP DEBUGGER : OCD
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
4.2.3. Message Buffer : MBR
The is message buffer is shown below.
It is a register to do writing and the demand control of the message for a semi-hosting.
MBR: Address 0BFA
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BUSY
DMAREQ
Reserved
Initial value
0
0
X
X
X
X
X
X
Attribute R,WX
R,W1
RX,W0 RX,W0
RX,W0
RX,W0
RX,W0
RX,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MB[7:0]
Initial value
X
X
X
X
X
X
X
X
Attribute RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
[bit15] BUSY (Message Buffer Busy) : Message Buffer Busy
It is a bit that busy detects the message buffer. It becomes "1" by writing in MBR.MB[7:0] bits, and it
becomes "0" by the message reading from the tool side. This bit is for reading only, and writing doesn't have
the influence in operation.
BUSY
Message buffer busy state
0
Non-busy state (initial value)
1
Busy state
[bit14] DMAREQ (DDMAMessage Handling Request) : DDMA message processing request bit
It is a bit that requests the method of processing the message to use DDMA. Only "1" writing of this bit is
effective, and "0" writing doesn't have the influence in operation.
DMAREQ
DDMA message processing
0
Doesn't request (initial value)
1
Requests
[bit7 to bit0] MB (Message Buffer) : Message Buffer
It is a bit to write the message data of one byte. This bit is only for writing. The reading value is irregular.
MB91520 Series
MN705-00010-1v0-E
2027