Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
DTSCR2: Address 12AA
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DMOD2 GTEN5 GTEN4
TMIF2
TMIE2
TMD8
TMD7
TMD6
Initial values
0
0
0
0
0
0
0
0
Attributes
R/W
R/W
R/W
R(RM1),
W
R/W
R/W
R/W
R/W
[bit7] DMOD2: Output polarity control bit
DMOD2
Function
0
Normal polarity output
1
Inverted polarity output
⋅
This bit is used to configure U/VW output in the dead time timer mode.
⋅
When this bit is set, output polarity of U/VW will be inverted.
Note:
This bit does not mean anything if the dead time timer mode is not selected. (TMD8: bit10=0)
[bit6] GTEN5: GATE signal control bit 5
GTEN5
Function
0
GATE signal will not be controlled by a compare output of the output compare.
(asynchronous mode)
1
GATE signal will be controlled by a compare output of the output compare.
(synchronous mode)
⋅
This bit is used to control the PPG timer's GATE signal output for the compare output of the output
compare.
⋅
If it is set to 0, GATE signal will not be output.
⋅
If it is set to 1, GATE signal will be output. PPG of the output destination can be selected from PSEL21,
PSEL20 of SIGCR20/21.
[bit5] GTEN4: GATE signal control bit 4
GTEN4
Function
0
GATE signal will not be controlled by a compare output of the output compare.
(asynchronous mode)
1
GATE signal will be controlled by a compare output of the output compare.
(synchronous mode)
⋅
This bit is used to control the PPG timer's GATE signal output for the compare output of the output
compare.
⋅
If it is set to 0, GATE signal will not be output.
⋅
If it is set to 1, GATE signal will be output. PPG of the output destination can be selected from PSEL21,
PSEL20 of SIGCR20/21.
MB91520 Series
MN705-00010-1v0-E
2061