Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.1. Division Configuration Register 0 : DIVR0 (Division
clock configuration Register 0)
The bit configuration of the division configuration register 0 is shown.
This register controls division of clocks.
DIVR0 : Address 0488
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DIVB[2:0]
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] DIVB[2:0] (Division ratio of Baseclock) : Base clock division setting
These bits configure a division in the area where the base clock is generated from the source clock as follows.
The CPU operation clock and the on-chip bus clock (HCLK) have the same frequency as that of the base
clock.
DIVB[2:0]
Division ratio
000
No divide (Initial value)
001
2 division
010
3 division
011
4 division
100
5 division
101
6 division
110
7 division
111
8 division
[bit4 to bit0] (Reserved)
MB91520 Series
MN705-00010-1v0-E
172