Fujitsu FR81S User Manual

CHAPTER 48: WAVEFORM GENERATOR

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : WAVEFORM GENERATOR

FUJITSU SEMICONDUCTOR CONFIDENTIAL

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This bit will be cleared when the dead timer interrupt clear signal is "H".

Notes:

If this bit is read by a read-modify-write (RMW) instruction, "1" is always read.

If a software clear (write of "0") or a clear by an interrupt clear signal ("H") and a hardware set occur at the

same time, the hardware set has a priority over the software clear or the clear by interrupt clear signal.

Then, this bit will be set.

[bit4] DTRIE1: 16-bit dead timer 1 reload interrupt enable bit

DTRIE1

Function

An interrupt will not be generated even when a reload occurs at the 16-bit dead timer.

An interrupt will be generated when a reload occurs at the 16-bit dead timer.

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This bit enables or disables the output of interrupts to the CPU.

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An interrupt request is generated when this bit and the interrupt request flag bit (DTIR: DTRIF1) are "1".

[bit3] DTRIF0: 16-bit dead timer 0 reload interrupt flag bit

DTRIF0

Function

Read

Write

No reload of the dead timer has been

detected.

This bit is cleared.

A reload of the dead timer has been detected.

This bit remains unaffected.

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For the 16-bit dead timer 0, if the timer is reloaded before it underflows, this bit will be set to "1".

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An interrupt request is generated when this bit and the interrupt request enable bit (DTIR: DTRIE0) are

"1".

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This bit is cleared when "0" is written to it. A write of "1" does not change this bit and has no influence

on others.

⋅

This bit will be cleared when the dead timer interrupt clear signal is "H".

Notes:

If this bit is read by a read-modify-write (RMW) instruction, "1" is always read.

If a software clear (write of "0") or a clear by an interrupt clear signal ("H") and a hardware set occur at the

same time, the hardware set has a priority over the software clear or the clear by interrupt clear signal. Then,

this bit will be set.

[bit2] DTRIE0: 16-bit dead timer 0 reload interrupt enable bit

DTRIE0

Function

An interrupt will not be generated even when a reload occurs at the 16-bit dead timer.

An interrupt will be generated when a reload occurs at the 16-bit dead timer.

⋅

This bit enables or disables the output of interrupts to the CPU.

⋅

An interrupt request is generated when this bit and the interrupt request flag bit (DTIR: DTRIF0) are "1".

[bit1, bit0] Reserved

Always write 0 to these bits.

MB91520 Series

MN705-00010-1v0-E

2065