Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
4.1.5. Waveform Control Register 1/2 (SIGCR1, SIGCR2)
The bit configuration for the waveform control register 1/2 is shown below.
The waveform control register 1/2 (SIGCR1, SIGCR2) is used to control the operating clock frequency, noise
cancel function valid settings, DTTI input valid settings, and DTTI interrupts.
SIGCR10: Address 12B1
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTIE
DTIF
NRSL
DCK2
DCK1
DCK0
NWS1
NWS0
Initial values
0
0
0
0
0
0
0
0
Attributes
R/W
R(RM1),
W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7] DTIE: DTTI input validating bit
DTIE
Function
0
Invalidate the DTTI input
1
Validate the DTTI input
⋅
This bit is used to validate the output level control DTTI signals for the RTO0 to RTO5 pins.
[bit6] DTIF: DTTI Interrupt flag bit
DTIF
Function
Read
Write
0
No interrupt request
This bit is cleared.
1
Interrupt request present
This bit remains unaffected.
⋅
This bit is an interrupt flag for the DTTI.
⋅
When the DTTI input becomes valid (DTIE: bit23=1) and "L" level of the DTTI is detected, this bit will
be set and an interrupt request will be generated.
⋅
When this bit is set to "0": This bit is cleared.
⋅
When this bit is set to "1": This bit remains unaffected.
⋅
This bit will be cleared when the DTTI interrupt clear signal is "H".
Notes:
If a read-modify-write (RMW) instruction is executed, "1" is always read.
When the noise cancel function becomes valid (NRSL: bit21=1) and a noise pulse is generated, this bit will
be set to "1".
If a software clear (write of "0") or a clear by an interrupt clear signal ("H") and a hardware set (DTTI "L"
level detection) occur at the same time, the hardware set has a priority over the software clear or the clear
by interrupt clear signal. Then, this bit will be set.
[bit5] NRSL: Noise cancel function validating bit
NRSL
Function
0
Noise cancel circuit of the DTTI input will be invalidated
1
Noise cancel circuit of the DTTI input will be validated
⋅
This bit is used for validating the noise cancel function.
⋅
The noise cancel circuit receives DTTI input signals until an overflow occurs at the counter while it
remains at the "L" level. The counter is a N-bit counter operated by the "L" level input.
⋅
Value for N will be either 2, 3, 4, or 5 based on the settings of the NWS1, NWS0: bit17, bit16.
MB91520 Series
MN705-00010-1v0-E
2068