Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
Pins and Bit Setting
Pin application table for RTO/GATE output state and bit settings is as follows:
Table 5-5 Pins and Bit Setting Application Table
GATE
signal
control bit
PPG output
enable bit
Real time
output
Compare
output
16-bit dead timer
Non-overlap
signal
GTEN0
PGEN0
RTO0
OUT0
16-bit dead timer 0
OUT1
GTEN1
PGEN1
RTO1
OUT1
16-bit dead timer 0
OUT1
GTEN2
PGEN2
RTO2
OUT2
16-bit dead timer 1
OUT3
GTEN3
PGEN3
RTO3
OUT3
16-bit dead timer 1
OUT3
GTEN4
PGEN4
RTO4
OUT4
16-bit dead timer 2
OUT5
GTEN5
PGEN5
RTO5
OUT5
16-bit dead timer 2
OUT5
Note:
The RTO0 and RTO1 are controlled by the TMD2 to TMD0 of the 16-bit dead timer state control register
(DTSCR0). The RTO2 and RTO3 are controlled by the TMD5 to TMD3 of the DTSCR1 register. The
RTO4 and RTO5 are controlled by the TMD8 to TMD6 of the DTSCR2 register.
Operation Timing
Operation timing of the waveform generator dead timer
Figure 5-1 Operation Timing of the Waveform Generator Dead Timer
CLK
TMD02-TMD00
100
B
000
B
0005
H
0000
H
TMRR0[15:0]
DCK2-DCK0
TR1
count_CLKP0
TM0[15:0]
5
4
3
2
1
0
5
4
3
2
1
0
UDF0
RTST01
RTST00
TM_RT1
TM_RT0
XXX
UUU
RT01(X)
RT00(U)
MB91520 Series
MN705-00010-1v0-E
2076