Fujitsu FR81S User Manual
CHAPTER 48: WAVEFORM GENERATOR
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
Non-overlap signal generation by the inverted polarity OUT1, OUT3, and
OUT5 control (TMD8 to TMD0 of the 16-bit dead timer control registers
(DTSCR0, DTSCR1, DTSCR2) are 100
(DTSCR0, DTSCR1, DTSCR2) are 100
B
)
Signal generation is executed by outputting U/V/W and X/Y/Z of the normal polarity non-overlap signal that
does not operate by minus control as X/Y/Z and U/V/W.
Figure 5-8 Non-overlap Signal Generation When MNS Bit of the Inverted Polarity DTMNS
Register Is 1 (Minus Setting)
TMRR0
setting value
Count value of 16-bit
dead timer 0
Time
Compare output 1
RTO0 (U)
<Register setting>
TCDT
: "XXXX
H
"
TCCS
: "X-XXXXXXX0X0XXXX---XXXX
B
"
CPCLR
: "XXXX
H
" (cycle setting)
OCCP0 to OCCP5
: "XXXX
H
" (compare value)
OCS01 toOCS45
: "- XX1XXXX XXXXXX11
B
"
DTCR0 to DTCR2
: "0XXXX100
B
"
TMRR0 to TMRR
: "XXXX
H
" (non-overlap timing setting)
DTMNS0
: "XX---111
B
"
SIGCR10
: "XXXXXX00
B
" (DTTI input and 16-bit dead timer count clock setting)
(Note) "X": Make a setting according to the operation.
RTO1 (X)
2 peripheral clock cycles
Pin name
RTO0(U)
RTO2(V)
RTO4(W)
RTO1(X)
RTO3(Y)
RTO5(Z)
Output signal
Delayed inverted signals are applied to the falling edge of compare output 1.
Delayed inverted signals are applied to the falling edge of compare output 3.
Delayed inverted signals are applied to the falling edge of compare output 5.
Delayed signals are applied to the rising edge of compare output 1.
Delayed signals are applied to the rising edge of compare output 3.
Delayed signals are applied to the rising edge of compare output 5.
MB91520 Series
MN705-00010-1v0-E
2084