Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
However, when CKS[1:0] ≠ CKM[1:0], these bits cannot be rewritten. When the clock oscillation which you
are trying to switch operations by these bits stops or is waiting for a stabilization (CMONR.xCRDY=0), this
bit cannot also be rewritten.
A direct switch from PLL/SSCG clock (PLLSSCLK) to the sub clock (SBCLK) or vice versa cannot be
performed.
Possible combinations for changing these bits are shown below.
CKS value before
change
Eligible values
Rewritten
conditions
Ineligible values
00
00, 01
MCRDY=1
11
10
PCRDY=1
01
00, 01
MCRDY=1
10
11
SCRDY=1
10
00
MCRDY=1
01,11
10
PCRDY=1
11
01
MCRDY=1
00,10
11
SCRDY=1
Do not write the values which cannot be rewritten.
MB91520 Series
MN705-00010-1v0-E
177