Fujitsu FR81S User Manual
CHAPTER 49: BUS DIAGNOSIS FUNCTION
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : BUS DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
5.1. Error detection
This section explains the Error detection of bus diagnosis function.
When the error is detected by the bus diagnosis, the direction of access address access when error is
detected is maintained in each bus diagnosis address register (BUSADR), RDWR bit in bus diagnosis status
register (BUSDISR).
Moreover, when the error by the write access is detected, the write to the resource is not done.
Address error detection
When the parity operation result of the bus address is an error, The address error detection sets "1" to
AER[3:0] bit in the bus diagnosis status register (BUSDISR).
AER[3:0] bit can be cleared by writing "1" to PECLR bit in this register.
Control error detection
When the parity operation result of the bus control is an error, the control error detection sets "1" to CNER
bit in the bus diagnosis status register (BUSDISR).
The CNER bit can be cleared by writing "1" to PECLR bit in this register.
Data error detection
When the parity operation result of the bus data is an error, the data error detection sets "1" in DER[3:0] bit
to which bus diagnosis status register (BUSDISR) responds according to the access size of the word, the
half-word, and the byte.
DER[3:0] bit can be cleared by writing "1" to PECLR bit in this register.
The error detection part of the "bus diagnosis status register (BUSDIGSR).DER[3:0]" is shown as follows.
(: Error detection is done. , -: Error detection is not done. )
Access size
Address
BUSDIAGSR0 (AHB: On-chip bus)
BUSDIAGSR1 (APB: 32bit peripheral bus)
BUSDIAGSR2 (R-bus: 16bit peripheral bus)
DER[0]
DER[1]
DER[2]
DER[3]
Data bit31-24 Data bit23-16 Data bit15-8
Data bit7-0
Word access
Addr+0
*
*
*
*
Half-word access Addr+0
-
-
Half-word access Addr+2
-
-
Byte access
Addr+0
-
-
-
Byte access
Addr+1
-
-
-
Byte access
Addr+2
-
-
-
Byte access
Addr+3
-
-
-
*:R-bus: The word access to 16bit peripheral bus are treated as 2-times half-word access. Therefore, only
the half-word access error that does the error detection in the beginning is notified to the register.
It is accessed in following order usually.
Upper half-word access (data bit31-16) --> lower half-word access (data bit15-0)
However, only the word access to the PPG and up/down counter is accessed in following order.
Lower half-word access (data bit15-0) --> upper half-word access (data bit31-16)
MB91520 Series
MN705-00010-1v0-E
2113