Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
4.5. Clock Source Monitor Register : CMONR (Clock
source MONitor Register)
The bit configuration of the clock source monitor register is shown.
This register displays a status and a source clock (SRCCLK) for each clock source.
You can confirm that the value set at CSELR is really reflected in the actual status by reading this register.
CMONR: Address 0511
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCRDY PCRDY MCRDY
Reserved
CKM[1:0]
Initial value
*
0
1
0
0
0
0
0
Attribute R,WX
R,WX
R,WX R0,WX R0,WX R0,WX R,WX
R,WX
*: This bit is initialized to “0”. But this bit is not initialized by the return from the watch mode
(power-shutdown).
Note:
If you have changed CSELR, do not write next value on CSELR until CMONR is equal to CSELR.
[bit7] SCRDY (Sub Clock ReaDY) : Sub clock ready
This bit shows the sub clock (SBCLK) status as follows.
SCRDY
Sub clock (SBCLK) status
0
Oscillation stops or in the oscillation stabilization wait status.
1
It is in the oscillation stabilization status and available for the source clock.
This bit cannot select a sub clock (SBCLK) as the source clock when this bit is set to "0".
Note:
SCRDY=1 may be read immediately after changing SCEN=1 to 0.
[bit6] PCRDY (PLL Clock ReaDY) : PLL clock ready
This bit shows the PLL/SSCG clock (PLLSSCLK) status as follows.
PCRDY
PLL/SSCG clock (PLLSSCLK) status
0
Oscillation stops or in the oscillation stabilization wait status.
1
It is in the oscillation stabilization status and available for the source clock.
This bit cannot select a PLL/SSCG clock (PLLSSCLK) as the source clock when this bit is set to "0".
MB91520 Series
MN705-00010-1v0-E
178