Fujitsu FR81S User Manual

CHAPTER 50: RAM DIAGNOSIS FUNCTION 

 

 

3. Configuration 

 

FUJITSU SEMICONDUCTOR LIMITED 

CHAPTER : RAM DIAGNOSIS FUNCTION 

FUJITSU SEMICONDUCTOR CONFIDENTIAL 

5 

This section explains the configuration of RAM diagnosis function. 

Figure 3-1 Block Diagram of XBS RAM Diagnosis Function (Configuration) 

 

TRUN

TASARX (TEST start address register)
TAEARX (TEST end address register)

Unique

pattern

generation

Checker

pattern

generation

March

pattern

generation

Test circuit

Initialization

pattern

generation

TEAR0X(TESTerror address register 0)

TEI

TCIE

TCI

TSTAT

OVFLW

TEIE

TYP1 TYP0

TYP2

TTCRX

(TEST diagnosis function register)

TTCRX

(TEST diagnosis

function register)

IRUN

ITYP

TICRX

(TEST initialization

function register)

ICIE

ICI

TICRX

(TEST initialization function register)

SRST

TSRCRX

(TEST soft reset

generation control register)

RST

RAM diagnosis

write data

RAM diagnosis

read data

TEAR1X(TESTerror address register 1)
TEAR2X(TESTerror address register 2)

ETYP0

ETYP2 ETYP1

FERR

TFECRX

(TEST false error gen eration

control register)

RAM diagnosis,

initialization

control circuit

Diagnosis

completed

Initialization completed

Indicate diagnosis

content

Indicate initialization content

Start address

Endaddress

Address signal

Unique

selection signal

Checker

selection signal

March

selection signal

Initialization

selection signal

Diagnosis execution signal

False error generation

process specify

False error generation start/stop

RAM access

control

Test control

RAM diagnosis end interrupt

RAM initialization completion interrupt

Error interrupt during RAM diagnosis

CODE0

KEY0 CODE1

KEY1

TKCCRX

(TEST key-code

control register)

Diagnosis start

Initialization start

Forced end

 

 

Figure 3-2 Block Diagram of Backup RAM Diagnosis Function (Construction) 

 

TRUN

TASARA (TEST start address register)
TAEARA (TEST end address register)

Unique

pattern

generation

Checker

pattern

generation

March

pattern

generation

Test circuit

Initialization

pattern

generation

TEAR0A(TESTerror address register 0)

T

EI

T

CIE

T

CI

T

STAT

OVFLW

T

EIE

T

YP1 TYP0

T

YP2

TTCRA

(TEST diagnosis function register)

TTCRA

(TEST diagnosis

function register)

IRUN

ITYP

TICRA

(TEST initialization

function register)

I

CIE

I

CI

TICRA

(TEST initialization function register)

S

RST

T

SRCRA

(TEST soft reset

generation control register)

RST

RAM diagnosis

write data

RAM diagnosis

read data

T

EAR1A(TESTerror address register 1)

T

EAR2A(TESTerror address register 2)

E

TYP0

E

TYP2 ETYP1

F

ERR

T

FECRA

(TEST false error gen eration

control register)

R

AM diagnosis,

initialization

control circuit

Diagnosis

completed

Initialization completed

I

ndicate diagnosis

content

Indicate initialization content

S

tart address

Endaddress

Address signal

Unique

selection signal

Checker

selection signal

March

selection signal

Initialization

selection signal

Di

agnosis execution signal

False error generation

process specify

False error generation start/stop

RAM access

control

T

est control

RAM diagnosis end interrupt

RAM initialization completion interrupt

Error interrupt during RAM diagnosis

C

ODE0

K

EY0 CODE1

K

EY1

TKCCRA

(TEST key-code

control register)

Diagnosis start

Initialization start

Forced end

 

 

 

MN705-00010-1v0-E

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