Fujitsu FR81S User Manual
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.3. TEST Error Address Register 2 XBS RAM : TEAR2X
This section explains the bit structure of TEST Error Address Register 2 XBS RAM.
Only when an error occurs in the address different from that held in TEAR0X and TEAR1X during RAM
diagnosis for XBS RAM, TEST error address register 2 (TEAR2X) holds that address.
•
TEAR2X: Address 3014
H
(Access: Byte, Half-word, Word)
31
30
29
28
27
26
25
24
BIT
TER2
TER1
TER0
Reserved
0
0
0
0
0
0
0
0
Initial values
R, WX
R, WX
R, WX
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
Attributes
23
22
21
20
19
18
17
16
BIT
Reserved
0
0
0
0
0
0
0
0
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
Attributes
15
14
13
12
11
10
9
8
BIT
Reserved
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
Initial values
R0, W0
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
Attributes
7
6
5
4
3
2
1
0
BIT
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Initial values
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
R, WX
Attributes
[bit31 to bit29] TER2 to TER0: Diagnosis error factor specification bits
During RAM diagnosis for XBS RAM, these bits hold a diagnosis pattern for which the error occurred. D14
to D0 are valid only when one of the bits is set to "1".
TER2
TER1
TER0
Function
0
0
0
D14 to D0 are invalid with no error generated
-
-
1
An error occurs during march diagnosis
-
1
-
An error occurs during checker diagnosis
1
-
-
An error occurs during unique diagnosis
These bits are initialized (cleared to "000") by hardware, using the RAM diagnosis start instruction as the trigger.
[bit28 to bit15] Reserved
Reserved bits. These bits read out "0". At writing, write "0".
MB91520 Series
MN705-00010-1v0-E
2132