Fujitsu FR81S User Manual
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
4.7. TEST Initialization Function Register XBS RAM :
TICRX
This section explains the bit structure of TEST Initialization Function Register XBS RAM.
The TEST initialization function register (TICRX) specifies the RAM initialization content, and holds the
initialization result and its status for XBS RAM.
•
TICRX: Address 301D
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
BIT
Reserved
ICIE
ICI
ITYP
IRUN
0
0
0
0
0
0
0
0
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R/W
R (RM1), W
R/W
R, WX
Attributes
[bit7 to bit4] Reserved
Reserved bits. These bits read out "0". At writing, write "0".
[bit3] ICIE: Interrupt enable bit for a RAM initialization end factor
ICIE
Function
0
Prohibition of an interrupt for a RAM initialization end factor
1
Enabling of an interrupt for a RAM initialization end factor
This bit is used to enable an interrupt for the RAM initialization end factor for XBS RAM.
"0": Prohibits an interrupt resulting from a RAM initialization end.
"1": Enables an interrupt resulting from a RAM initialization end. The interrupt signal (RAM
initialization complete interrupt) is output with TICRX.ICI= 1.
[bit2] ICI: RAM initialization end bit
ICI
Function
0
Read: The RAM initialization does not end.
Write: Flag clearing.
1
Read: The RAM initialization ended.
Write: No influence on the operation.
If RAM initialization end for XBS RAM is detected, this bit is set to "1".
When "0" is written in this bit, it is cleared to "0". However, writing "1" to this bit is invalid and this bit
holds the previous value.
"1": Set when a RAM initialization is ended. (It will not be set for forced termination by a key code)
"0": Set when "0" is written.
Note:
At read access of the read-modify-write instruction, "1" is always read.
MB91520 Series
MN705-00010-1v0-E
2139