Fujitsu FR81S User Manual
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
4.9. TEST Fake Error Generation Control Register XBS
RAM : TFECRX
This section explains the bit structure of TEST Fake Error Generation Control Register XBS
RAM.
TEST fake error generation control register (TFECRX) generates a fake error in RAM diagnosis operation
for XBS RAM. Error generation can be specified which of RAM diagnosis operations.
•
TFECRX: Address 301C
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
BIT
Reserved
FERR
ETYP2
ETYP1
ETYP0
0
0
0
0
0
0
0
0
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R/W
R/W
R/W
R/W
Attributes
[bit7 to bit4] Reserved
Reserved bits. These bits read out "0". At writing, write "0".
[bit3] FERR: Fake error enable bit for RAM diagnosis
FERR
Function
0
Prohibition of a fake error (normal operation)
1
Enabling of a fake error
This bit is used to enable a fake error for RAM diagnosis for XBS RAM.
"0": Prohibits a fake error. (normal operation)
"1": Enables a fake error. Data write including intentional error is enabled following ETYP2 to ETYP0.
[bit2 to bit0] ETYP2 to ETYP0: Fake error process specification bits
These bits are used to specify a process to generate a fake error.
ETYP2
ETYP1
ETYP0
Process to generate a fake error
-
-
1
March diagnosis
-
1
-
Checker diagnosis
1
-
-
Unique diagnosis
MB91520 Series
MN705-00010-1v0-E
2142