Fujitsu FR81S User Manual
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
4.14. TEST Start Address Register BACKUP-RAM : TASARA
This section explains the bit structure of TEST Start Address Register BACKUP-RAM.
TEST start address register (TASARA) specifies the start address of RAM diagnosis and initialization for
Backup RAM.
•
TASARA: Address 303E
H
(Access: Byte, Half-word, Word)
15
14
13
12
11
10
9
8
BIT
Reserved
ST10
ST9
ST8
0
0
0
0
0
0
0
0
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R/W
R/W
R/W
Attributes
7
6
5
4
3
2
1
0
BIT
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
0
0
0
0
0
0
0
0
Initial values
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attributes
[bit15 to bit11] Reserved
Reserved bit. These bits read out "0". At writing, write "0".
[bit10 to bit0] ST10 to ST0: RAM diagnosis start address bits
These bits are used to specify the address from which the RAM diagnosis and initialization start for Backup
RAM.
Note:
Setting of a value outside the Backup RAM area and a value that sets TASARA.ST10 to ST0 >
TAEARA.ED10 to ED0 is disabled.
Note:
The above-mentioned address is an offset of the word length.
The absolute address is calculated by adding the base address to the offset address where lower two bits
were added.
(Absolute address) = (0000_4000
H
) + (Offset address set with TASARA + 2'b00)
MB91520 Series
MN705-00010-1v0-E
2150