Fujitsu FR81S User Manual
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
4.18. TEST Soft Reset Generation Control Register
BACKUP-RAM : TSRCRA
This section explains the bit structure of TEST Soft Reset Generation Control Register
BACKUP-RAM.
The TEST soft reset generation control register (TSRCRA) specifies the generation of the software reset for
initializing internal circuits for Backup RAM's RAM diagnosis.
•
TSRCRA: Address 3044
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
BIT
SRST
Reserved
0
0
0
0
0
0
0
0
Initial values
R0, W
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
Attributes
[bit7] SRST: Software reset enabling bit
SRST
Function
0
Prohibition of a software reset
1
Enabling of a software reset
This bit is used to enable a software reset for the internal circuit for RAM diagnosis for Backup RAM.
This bit reads out "0".
"1": Reset pulses occur for 4τ only and the internal circuit for RAM diagnosis except this register is
reset.
[bit6 to bit0] Reserved
Reserved bits. These bits read out "0". At writing, write "0".
MB91520 Series
MN705-00010-1v0-E
2157