Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
4.7. Sub Timer Control Register : STMCR (Sub clock TiMer
Control Register)
The bit configuration of the sub timer control register is shown.
This register controls the sub timer which runs with the sub clock.
STMCR: Address 0513
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
STIF
STIE
STC
STE
Reserved
STS[2:0]
Initial value
0
0
0
0
0
1
1
1
Attribute R(RM1),W
R/W
R(RM0),W
R/W
R0,WX
R/W
R/W
R/W
Because the sub timer is used for generating the oscillation stabilization wait time for the sub clock (SBCLK),
it can be used only after the sub clock oscillation is stabilized.
The sub timer is cleared when the sub clock oscillation stops (SCEN=0) or it is in the stop mode.
When the operation of the sub timer is not allowed (STE=0), the sub timer stops except that it is waiting for a
sub clock oscillation stabilization. The write operation to this register becomes enabled only when SCRDY=1
except for STIE. Thus a sub timer clear executed by STC=1 in sub clock oscillation stabilization wait status
(SCEN=1 and SCRDY=0) is not effective.
When the sub timer stops (STE=0) it will be cleared and while being cleared STC=1 will be read out. At that
time the sub timer interrupt flag is not set. The sub timer overflow period (STS[2:0]) should be changed at the
time when the sub timer stops (STE=0).
When rewriting STE=1 with 0, the sub timer will continue to operate until STC is set to "0". In this interval,
the sub timer interrupt flag may turn to "1". When writing STC=1, the sub timer will continue to operate until
STC is set to "0". In this interval, the sub timer interrupt flag may turn to "1". If a STE=0 to 1 rewrite and a
STC=1 write occur at the same time, the operation starts after a clear takes place, so the start will be delayed.
[bit7] STIF (Sub clock Timer Interrupt Flag) : Sub timer interrupt flag
The flag to indicate that an overflow happens in the interval for which the sub timer has selected.
When the STIE bit is "1" and this bit is set, a sub timer interrupt request is generated.
Clear factor
⋅
"0" write
⋅
A DMA transfer is generated by the sub timer interrupt.
Set factor
⋅
An overflow occurred in the interval set by STS[2:0].
⋅
The end of oscillation stabilization wait time of the sub clock after setting SCEN=0
to 1.
⋅
The ends of oscillation stabilization wait time of the sub clock after exiting the stop
mode.
Writing "1" to this bit is ineffective.
When the STIE bit is set to "0", this bit will not be cleared by DMA transfer.
For read-modify-write instructions, "1" will be read out.
If a set factor and a clear factor occur at the same time, the set factor will take precedence.
MB91520 Series
MN705-00010-1v0-E
182