Fujitsu FR81S User Manual

CHAPTER 51: TIMING PROTECTION UNIT

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : TIMING PROTECTION UNIT

FUJITSU SEMICONDUCTOR CONFIDENTIAL

[bit23] GLBPSE (Global Prescaler Enable) : Global prescaler operation permission

The operation of global prescaler is controlled. All timers are not the operation of the count at the operation

prohibition.

DLBPSE

Global Prescaler

Operation prohibition

Operation permission

[bit22] (Reserved) : (Reserved bit)

These bits are reserved bit. When writing to those bits, 0 must be set. The readout value is 0.

[bit21 to bit16] GLBPS[5:0] (Global Prescaler Bits) : Global prescaler dividing value setting

These bits are used to specify the divider setting of the clock that supplied to all timers in common. Update

of the bits has to be done when TPUCFG.GLBPSE=0 (timer operation disabled).

In TPU, the system clock (HCLK) is divided with global prescaler and the clock is supplied to each timer.

GLBPS[5:0] indicates the value of dividing frequency as it is.

GLBPS[5:0]

Global Prescaler Output

000000

HCLK / 1

000001

HCLK / 2

000010

HCLK / 3

…

111111

HCLK / 64

[bit15 to bit1] (Reserved) : (Reserved bit)

These bits are reserved bits. When writing to those bits, 0 must be set. The readout value is 0.

[bit0] INTE (TPU Interrupt Enable) : TPU interrupt enable

This bit is used to specify the interrupt enable of TPU.

INTE

TPU Interrupt

Interrupt disable

Interrupt enable

MB91520 Series

MN705-00010-1v0-E

2178