Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
4.8. PLL Setting Register : PLLCR (PLL Configuration
Register)
The bit configuration of the PLL setting register is shown.
This register configures the multiplication rate or division ratio in the PLL/SSCG clock oscillation circuit and
the oscillation stabilization wait time.
PLLCR: Address 0514
H
(Access : Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
POSW[3:0]
PDS[3:0]
Initial value
1
1
1
1
0
0
0
0
Attribute R1,WX
R,W
R,W
R,W
R,W
R,W
R,W
R,W
This register configures the multiplication rate in the PLL/SSCG clock oscillation circuit generating the
PLL/SSCG clock (PLLSSCLK) from the main clock (MCLK).
When PLL/SSCG clock oscillation is allowed (CSELR.PCEN=1), writing to this register has no effect.
[bit15, bit14] (Reserved)
Always write "0".
[bit13] (Reserved)
[bit12 to bit8] (Reserved)
Always write "0".
MB91520 Series
MN705-00010-1v0-E
184