Fujitsu FR81S User Manual
CHAPTER 52: CLOCK MONITOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK MONITOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
4. Registers
This section explains the registers of clock monitor
Table 4-1 Register Map
Address
Register
Register function
+0
+1
+2
+3
0x04A8
Reserved
Reserved
CSCFG
CMCFG
Clock Monitor Configuration Registers
4.1. Clock Monitor Configuration Registers : CMCFG
THE clock monitor configuration registers are shown.
•
CMCFG: Address 04AB
H
(Access: Byte, Half-word, Word)
bit 7
6
5
4
3
2
1
0
CMPRE3
CMPRE2
CMPRE1
CMPRE0
CMSEL3
CMSEL2
CMSEL1
CMSEL0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit7 to bit4] CMPRE3 to CMPRE0 (Output Frequency Prescaler Bits)
Division ratio setting of selected source clock by CMSEL bits.
CMPRE3 CMPRE2 CMPRE1 CMPRE0
Clock frequency output to the MONCLK pin
0
0
0
0
Source clock divided by 1 (Initial value)
0
0
0
1
Source clock divided by 2
0
0
1
0
Source clock divided by 3
0
0
1
1
Source clock divided by 4
0
1
0
0
Source clock divided by 5
0
1
0
1
Source clock divided by 6
0
1
1
0
Source clock divided by 7
0
1
1
1
Source clock divided by 8
1
0
0
0
Source clock divided by 9
1
0
0
1
Source clock divided by 10
1
0
1
0
Source clock divided by 11
1
0
1
1
Source clock divided by 12
1
1
0
0
Source clock divided by 13
1
1
0
1
Source clock divided by 14
1
1
1
0
Source clock divided by 15
1
1
1
1
Source clock divided by 16
MB91520 Series
MN705-00010-1v0-E
2201