Fujitsu FR81S User Manual
CHAPTER 52: CLOCK MONITOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK MONITOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
[bit3 to bit0] CMSEL3 to CMSEL0 (Output Source Clock Selection Bits)
Selected source clock for output signal of MONCLK pin.
CMSEL3 CMSEL2 CMSEL1 CMSEL0
Clock source output to MONCLK pin
0
0
0
0
MONCLK output disabled (high impedance state)
(initial value)
0
0
0
1
Main oscillation before CSV
0
0
1
0
CR oscillation
0
0
1
1
Main oscillation after CSV
0
1
0
0
Setting Prohibition
0
1
0
1
Setting Prohibition
0
1
1
0
Setting Prohibition
0
1
1
1
Setting Prohibition
1
0
0
0
PLL output
1
0
0
1
SSCG output
1
0
1
0
PLL output after CAN prescaler (CAN system clock)
1
0
1
1
CCLK
1
1
0
0
HCLK
1
1
0
1
PCLK1(Spread peripheral clock)
1
1
1
0
PCLK2 (Peripheral clock after spread/ non spread selection)
1
1
1
1
TCLK
•
CSCFG: Address 04AA
H
(Access: Byte, Half-word, Word)
bit 7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
MONCKI
Reserved
0
0
0
0
0
0
0
0
Initial value
R/W0
R0,WX
R/W0
R/W
R/W0
R/W0
R/W0
R/W0
Attribute
[bit7 to bit5] Reserved
This bit is reserved. Always set this bit to "0" when writing.
[bit4] MONCKI : Clock Monitor MONCLK Inverter
MONCKI
Function
0
MONCLK mark level is low level (initial value)
1
MONCLK mark level is high level
[bit3 to bit0] Reserved
This bit is reserved. Always set this bit to "0" when writing.
MB91520 Series
MN705-00010-1v0-E
2202