Fujitsu FR81S User Manual
CHAPTER 52: CLOCK MONITOR
5. Operation Description
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK MONITOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
5. Operation Description
This section explains operation description of clock monitor
Clock division example
Clock switching sequence
CLKP
CLKP
CMSEL
Source clock
frequency
divided by 1/n
MONCLK pin
(MONCKI = 0)
MONCLK pin
MONCLK pin
(MONCKI = 1)
Source clock
1/2
1/2
1/3
1/4
1/8
1/15
1/16
0000
High impedance state
1
2
3
4
5
6
7
High impedance stat
0000
1011
High impedance state
High impedance stat
1. The MONCLK pin is in the high impedance state.
2. CMSEL is set to the selected clock (prescaler) from 0000
B
(no clock selected).
3. The MONCLK pin is set to the output "L" status (or "H" output if MONCKI is set to "1") for the duration of
one internal (prescaled) clock.
4. After one period of the selected (prescaler) internal clock, MONCLK outputs the selected (prescaler)
internal clock.
5. CMSEL is set to 0000
B
(no clock selected) from the selected clock (prescaler).
6. The MONCLK pin is set to the output "L" status (or "H" output if MONCKI is set to "1") for the duration of
one internal (prescaled) clock.
7. The MONCLK pin switches to the high impedance state.
MB91520 Series
MN705-00010-1v0-E
2203