Fujitsu FR81S User Manual

CHAPTER 5: CLOCK

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : CLOCK

FUJITSU SEMICONDUCTOR CONFIDENTIAL

4.10. PLL Oscillation Timer Control Register : PTMCR (PLL

clock osc TiMer Control Register)

The bit configuration of the PLL Oscillation timer control register is shown.

The timer that works with the main clock that does PLL/SSCG clock oscillation stabilization wait is

controlled.

The PLL/SSCG clock oscillation stabilization wait timer is used only at the oscillation stabilization wait time

of the PLL/SSCG clock.

The PLL/SSCG clock oscillation stabilization wait time becomes time set by PLLCR:POSW[3:0].

When PLL/SSCG clock oscillation is enabled(CSELR.PCEN="1"), PLL/SSCG clock stabilization timer

starts counting up. After the oscillation stabilization time elapses, PLL/SSCG clock stabilization timer stops.

Moreover, when PLL/SSCG clock oscillation stop (CSELR.PCEN ="0") is done, it is cleared.



PTMCR: Address 0517

(Access : Byte, Half-word, Word)

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

PTIF

PTIE

Reserved

Initial value

Attribute

R(RM1),W

R/W

R0,WX

[bit7] PTIF (Pll clock osc wait Timer Interrupt Flag) : PLL oscillation stabilization wait timer interrupt

flag

It is a flag that shows that the overflow at the time set by PLL oscillation stabilization wait selection (PLLCR:

POSW [3:0]) was generated. If this bit is set when the PTIE bit is "1", PLL/SSCG clock oscillation

stabilization wait timer interrupt request is generated.

Clear

factor

⋅

"0" write

⋅

Generation of DMA transfer with PLL/SSCG oscillation stabilization wait timer

Set factor

⋅

End of the oscillation stabilization wait time for PLL/SSCG clock oscillation

stabilization wait clock after PCEN=0→1

The "1" writing in this bit has no effect.

When the PTIE bit is ‘0', the clearness of this bit by the DMA forwarding is not done.

In the read modify write instruction, "1" is read.

The set factor is given priority when a set factor and a clear factor are generated at the same time.

[bit6] PTIE (Pll clock osc wait Timer Interrupt Enable) : PLL oscillation stabilization wait timer interrupt

enable

The interrupt by the overflow of PLL/SSCG clock oscillation stabilization wait timer is controlled as follows.

PTIE

Operation

Interrupt disabled (Initial value)

Interrupt enabled

(The interrupt request is output when the PTIF bit is "1".)

[bit5 to bit0] (Reserved)

MB91520 Series

MN705-00010-1v0-E

189