Fujitsu FR81S User Manual
APPENDIX
A. I/O Map
FUJITSU SEMICONDUCTOR LIMITED
APPENDIX
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
Address
Address offset value / Register name
Block
+0
+1
+2
+3
0017C8
H
SCR3/(IBCR3) [R/W]
B,H,W
0--00000
SMR3[R/W] B,H,W
000-00-0
SSR3[R/W] B,H,W
0-000011
ESCR3/(IBSR3)[R/W]
B,H,W
00000000
Multi-UART3
*1 Byte access is
possible only for
access to lower 8
bits.
*2 Reserved
because I
2
C mode
is not set
immediately after
reset.
*3 Reserved
because CSIO
mode is not set
immediately after
reset.
*4 Reserved
because LIN2.1
mode is not set
immediately after
reset.
0017CC
H
― /(RDR13/(TDR13))[R/W] H,W
-------- -------- *3
RDR03/(TDR03)[R/W] B,H,W
-------0 00000000 *1
0017D0
H
SACSR3[R/W] B,H,W
0----000 00000000
STMR3[R] B,H,W
00000000 00000000
0017D4
H
STMCR3[R/W] B,H,W
00000000 00000000
― /(SCSCR3/SFUR3)[R/W] B,H,W
-------- -------- *3 *4
0017D8
H
― /(SCSTR33)/
(LAMSR3)
[R/W] B,H,W
-------- *3
― /(SCSTR23)/
(LAMCR3)
[R/W] B,H,W
-------- *3
― /(SCSTR13)/
(SFLR13)
[R/W] B,H,W
-------- *3
― /(SCSTR03)/
(SFLR03)
[R/W] B,H,W
-------- *3
0017DC
H
―
― /(SCSFR23)
[R/W] B,H,W
-------- *3
― /(SCSFR13)
[R/W] B,H,W
-------- *3
― /(SCSFR03)
[R/W] B,H,W
-------- *3
0017E0
H
―/(TBYTE33)/
(LAMESR3)
[R/W] B,H,W
-------- *3
―/(TBYTE23)/
(LAMERT3)
[R/W] B,H,W
-------- *3
―/(TBYTE13)/
(LAMIER3)
[R/W] B,H,W
-------- *3
TBYTE03/(LAMRID3)
/
(LAMTID3)
[R/W] B,H,W
00000000
0017E4
H
BGR3[R/W] H, W
00000000 00000000
― /(ISMK3)[R/W]
B,H,W
-------- *2
― /(ISBA3)[R/W]
B,H,W
-------- *2
0017E8
H
FCR13[R/W]
B,H,W
---00100
FCR03[R/W]
B,H,W
-0000000
FBYTE3[R/W] B,H,W
00000000 00000000
0017EC
H
FTICR3[R/W] B,H,W
00000000 00000000
―
―
MB91520 Series
MN705-00010-1v0-E
2245