Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
30
4.12. PLL/SSCG Output Clock Division Setting Register :
CCPSDIVR (CCtl Pll/Sscg clock DIVision Register)
The bit configuration of the PLL/SSCG output clock division setting register is shown.
It is a register that sets the ratio of dividing frequency of the PLL/SSCG clock.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCPSDIVR: Address 0523
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PODS[2:0]
Reserved
SODS[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R/W
R/W
R/W
R0,WX
R/W
R/W
R/W
[bit7] (Reserved)
[bit6 to bit4] PODS (Pll Oscillator Divider selection) : Selection of PLL macro oscillation clock dividing
frequency ratio
The ratio of dividing frequency of the PLL clock is set.
PODS[2:0]
Dividing frequency ratio setting
000
PLL clock = PLL macro oscillation clock /2
001
PLL clock = PLL macro oscillation clock /4
010
PLL clock = PLL macro oscillation clock /6
011
PLL clock = PLL macro oscillation clock /8
100
PLL clock = PLL macro oscillation clock /10
101
PLL clock = PLL macro oscillation clock /12
110
PLL clock = PLL macro oscillation clock /14
111
PLL clock = PLL macro oscillation clock /16
Note:
It is only dividing of the even number in the setting by this bit. The odd number dividing frequency cannot be
set. Duty of the output clock becomes 50%.
Please set for the PLL clock to become 80MHz or less. (The operation of 80MHz or more is not guaranteed.)
[bit3] (Reserved)
MB91520 Series
MN705-00010-1v0-E
191