Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
4.14. SSCG Feedback Division Setting Register 0 :
CCSSFBR0 (CCtl SScg FB clock division Register 0)
The bit configuration of the SSCG feedback division setting register 0 is shown.
It is a register that sets multiple ratio of SSCG.
The multiple ratio of SSCG becomes P × N together with the setting of CCSSFBR1.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCSSFBR0: Address 0526
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
NDIV[5:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, bit6] (Reserved)
[bit5 to bit0] NDIV[5:0] (sscg feedback input N-DIVider ratio settings) : SSCG macro FB input N
dividing frequency ratio setting
It sets the SSCG multiple ratio N.
NDIV[5:0]
Dividing frequency ratio setting
000000
Setting is prohibited
000001
2
000010
3
…
……
111101
62
111110
63
111111
Setting is prohibited
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
MB91520 Series
MN705-00010-1v0-E
194