Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
34
4.15. SSCG Feedback Division Setting Register 1 :
CCSSFBR1 (CCtl SScg FB clock division Register 1)
The bit configuration of the SSCG feedback division setting register 1 is shown.
It is a register that sets the multiple ratio P of SSCG. The multiplication ratio of SSCG becomes P × N along
with the setting of CCSSFBR0.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCSSFBR1: Address 0527
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PDIV[4:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] (Reserved)
[bit4 to bit0] PDIV[4:0] (sscg feedback input P-DIVider ratio settings) : SSCG macro FB input P
divider frequency ratio setting
It sets the SSCG multiple ratio P.
PDIV[4:0]
Dividing frequency ratio setting
00000
1
00001
2
00010
3
…
……
11101
30
11110
31
11111
Setting is prohibited
A set value is limited. See "5.1.4 Limitations when PLL/SSCG Clock is used" when you set it.
MB91520 Series
MN705-00010-1v0-E
195