Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
42
4.21. RTC/PMU Clock Selection Register : CCRTSELR (CCtl
RTc pmu clock Selection Register)
The bit configuration of the division setting register 0 is shown.
Selects RTC/PMU source.
CCRTSELR : Address 0530
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CST
Reserved
CSC
Initial value
*
0
0
0
0
0
0
*
Attribute R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
*: These bits are initialized to “0”. But these bits are not initialized by the return from the watch mode
(power-shutdown).
[bit7] CST (Clock source selection STatus monitor): Clock source selection status monitor
A time lag by clock switch occurs until the CSC register is written and then the clock switch completes.
Whether the switch completes or not is monitored by this bit.
CST
Monitor
0
The completion of clock switch
1
During clock switch
Note:
Normally, switch completes by main clock × about 3 cycles + sub clock × about 3 cycles.
[bit6 to bit1] (Reserved)
[bit0] CSC (Clock SourCe selection) : Clock source selection
Selects clock of RTC/PMU.
CSC
Clock source
0
Main oscillation clock
1
Sub oscillation clock
Note:
The CSC register can be rewritten only when SCRDY=1 and MCRDY=1.
MB91520 Series
MN705-00010-1v0-E
203