Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
43
Notes:
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It takes main clock × about 3 cycles + sub clock × about 3 cycles until the switch operation of RTC and
PMU clock completes after rewriting the CSC register. When main clock and sub clock oscillation are
stopped during the switching operation, the switching operation does not complete correctly. The
oscillation must always be stooped in the status that the CST register is "0" (the status of the completion
of switching).
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The CSC bit is not initialized by the return from the standby watch mode (power-shutdown). Moreover,
any reset factors other than those, caused by power on reset/internal low-voltage reset/RSTX-NMIX
simultaneous assertion, cannot be accepted because an internal reset signal is generated while returning
from the standby watch mode (power-shutdown). At this time the CSC bit is not initialized. Initialize
this bit in case of need, when the reset signal comes from RSTX terminal input or external low-voltage
detection is flagged after the return from power-shutdown.
MB91520 Series
MN705-00010-1v0-E
204