Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
47
4.24. Sync/Async Control Register : SACR
The bit configuration of the sync/async control register is shown.
Selects the peripheral clock.
SACR : Address 1000
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
M
Initial value
1
1
1
1
1
1
1
0
Attribute R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R1,WX
R/W
[bit7 to bit1] (Reserved)
[bit0] M : Synchronous/asynchronous setting register of peripheral clock
The peripheral clock is switched when CPU selects the SSCG clock.
M
Synchronous/asynchronous setting
0
Synchronous (PLL/SSCG clock for CPU/peripheral)
1
Asynchronous (PLL/SSCG clock for CPU, PLL clock for peripheral)
MB91520 Series
MN705-00010-1v0-E
208