Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
48
4.25. Peripheral Interface Clock Divider : PICD
The bit configuration of peripheral interface clock divider is shown.
The setting of dividing frequency of the peripheral clock is done.
PICD : Address 1001
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PDIV[3:0]
Initial value
1
1
1
1
0
0
1
1
Attribute R1,WX R1,WX
R1,WX
R1,WX
R/W
R/W
R/W
R/W
[bit7 to bit4] (Reserved)
[bit3 to bit0] PDIV[3:0] : Sets peripheral clock division rate
The ratio of dividing frequency of the peripheral clock (PCLK2) is set from the PLL clock (PLLCLK) [non
spread spectrum clock] at SACR.M=1.
PDIV[3:0]
PLL clock (PLLCLK)[non spread spectrum clock]
→ PCLK2 division rate
0000
No divide
0001
2 division
0010
3 division
0011
4 division (initial value)
0100
5 division
0101
6 division
0110
7 division
0111
8 division
1000
9 division
1001
10 division
1010
11 division
1011
12 division
1100
13 division
1101
14 division
1110
15 division
1111
16 division
MB91520 Series
MN705-00010-1v0-E
209