Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
57
5.1.4. Limitations when PLL/SSCG Clock is used
The limitations of the PLL/SSCG clock used are shown.
Use it according to the following limitations when you use the PLL/SSCG clock.
Clock Control PLL Clock Frequency
Frequency
(max)
FCTLR:FAW CCPSSELR:
PCSEL
Remarks
80MHz
00
0
Note:
Set PLLCR or CCPSDIVR and CCPLLFBR so as not to exceed frequency (max).
Microcontroller Unit Clock Control SSCG Clock Frequency
Frequency
(max)
FCTLR:
FAW
CCPSSELR:
PCSEL
CCSSCCR0:
SSEN
CCSSCCR0:
SMODE
CCSSCCR1:
RATESEL
Remarks
72MHz
00
1
1
0
000 to 110
Down Spread
72MHz
00
1
1
1
000
Center Spread
(0.5%)
72MHz
00
1
1
1
010
Center Spread (1%)
72MHz
00
1
1
1
011
Center Spread (2%)
71MHz
00
1
1
1
100
Center Spread (3%)
71MHz
00
1
1
1
101
Center Spread (4%)
70MHz
00
1
1
1
110
Center Spread (5%)
80MHz
01
1
0
0/1
000 to 110
Spread 0%
80MHz
00
1
0
0/1
000 to 110
Spread 0%
Note:
Set CCPSDIVR, CCSSFBR0 and CCSSFBR1 so as not to exceed frequency (max).
Relation between Modulation Rate and Division Ratio when SSCG is Used
CCSSCCR1:RATESEL[2:0]
SSSCR1:RATESEL[2:0]
CCSSFBR0:NDIV[5:0]
SDIVCR0:NDIV[5:0]
Modulation rate
Set
value
Range of
division ratio
Set value
lower limit
Set value
upper limit
0.50%
00x
8 - 60
7
H
3B
H
1.00%
010
8 - 60
7
H
3B
H
2.00%
011
8 - 48
7
H
2F
H
3.00%
100
8 - 31
7
H
1E
H
4.00%
101
8 - 23
7
H
16
H
5.00%
110
8 - 18
7
H
11
H
MB91520 Series
MN705-00010-1v0-E
218