Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
61
5.2.3. End of the Stabilization Wait Time
The end of the stabilization wait time is shown.
The operations are stopped while the clock which is selected as a source clock is the status of the oscillation
stabilization wait time. The operations restart after the end of the oscillation stabilization wait time. You can
verify that the clock which is not selected as the source clock has entered the oscillation stabilization wait
time by checking the value of the ready bit corresponding to each clock for CMONR register when each clock
is enabled.
Displays the clock oscillation stabilization wait status and the oscillation stabilization status
⋅
Main clock
: CMONR:MCRDY ="0" ,
CMONR:MCRDY ="1"
⋅
PLL/SSCG clock (PLLSSCLK) : CMONR:PCRDY ="0" ,
CMONR:PCRDY ="1"
⋅
Sub clock (SBCLK)
: CMONR:SCRDY ="0" ,
CMONR:SCRDY ="1"
MB91520 Series
MN705-00010-1v0-E
222