Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
83
(2) F-divider must be set so that the PMU clock frequency become 32kHz or less.
The PMU clock is used to control the power switch, and the frequency of 32kHz or less is recommended for
the reasons for the stabilization at the pressure rising time when the power supply is input etc.
As for the PMU clock, the main clock is selected for CCRTSELR:CSC=0 as a source clock. Please set the
CCPMUCR0:FDIV register so that the frequency of the PMU clock may become 32kHz or less. The machine
of F divider frequency does not influence operation for CCRTSELR:CSC=1.
FDIV[1:0]
Division rate
Target main oscillation
frequency
00
128 division(initial value)
4MHz
01
256 division
8MHz
10
384 division
12MHz
11
512 division
16MHz
(3) G-divider must be set so that PMU clock frequency become 1/4 of the peripheral clock frequency
(PCLK1). Signal transfer between peripheral clock (PCLK) and PMU clock (PMUCLK) needs 4 PMU clock
cycles.
When the source clock of peripheral clock(PCLK1) is sub oscillation clock (CMONR.CKM=10), the
frequency of peripheral clock(PCLK1) should be set quadruple (or more higher) frequency of PMU clock. It
can be set by CCPMUCR1.GDIV register.
When the source clock of peripheral clock(PCLK1) is main oscillation clock (CMONR.CKM=00 or
CMONR.CKM=01). If the frequency of peripheral clock(PCLK1) is slower than 128kHz (32kHz × 4),
CCPMUCR1.GDIV register should be set as same.
GDIV[4:0]
Division ratio
00000
No divide (initial value)
00001
2 division
11110
31 division
11111
32 division
[Reference]
The frequency of the peripheral clock (PCLK1) can be calculated by the following expressions.
Peripheral clock (PCLK1) frequency=(Clock frequency selecting it by CMONR.CKM) / (DIVR0.DIVB[2:0]
division ratio) /(DIVR2.DVP[3:0] division ratio)
MB91520 Series
MN705-00010-1v0-E
244