Fujitsu FR81S User Manual
CHAPTER 7: RESET
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
2. Features
This section explains features of the reset.
This product, which has the following reset factors, issues a reset by accepting each factor to initialize the
components in the device.
⋅
Power-on reset
⋅
RSTX pin Input
⋅
Watchdog reset 0 (Software watchdog)
⋅
Watchdog reset 1 (Hardware watchdog)
⋅
Software reset
⋅
Illegal standby mode transition detection reset
⋅
Flash security violation
⋅
Internal low-voltage detection
⋅
External low-voltage detection
⋅
Clock supervisor reset
⋅
Recovery reset from stand by (power shutdown)
Other than the case of irregular reset (see "4.1 Reset Source Register : RSTRR (ReSeT Result Register)"), the
contents of memory being accessed by the reset (RAM, Flash) will not be destroyed since all resets are issued
once the completion of all bus accesses have been confirmed.
To issue a forced reset in case the bus does not return the response within a certain time frame, the device
waits for the reset issue delay counter. If there is no response within the specified time frame, a reset will be
issued whether or not the bus has responded. (Reset timeout)
See "CHAPTER : CLOCK SUPERVISOR" for clock supervisor reset.
MB91520 Series
MN705-00010-1v0-E
257