Fujitsu FR81S User Manual
CHAPTER 7: RESET
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
Figure 3-2 Configuration Diagram of Reset (Reset Control)
Figure 3-3 Generation Diagram of Illegal Standby Mode Transition Detection Reset Factor
CPUAR:
PSTF
CPUAR:
PSTRE
PSTRE
set
When the PLL/SSCG clock is
selected as a clock source
Transition to watch mode or
stop mode is generated
Illegal standby mode
transition detection
reset factor
Wa tchdog rese t 1
Generate rese t
Factor ext end counter
Extend counter
Initialize rese t
(INI T)
Extend counter
Rese t
(RST)
SRST
Delay counter
RDLY
8bit
2bit
S
4bit
4bit
PCLK
: bit nam e of regis ter
Wa tchdog reset 0
Delay
selector
R
IRRST
ERS T
WD G0
WD G1
SRST
RS TCR
RS TCR
RS TRR
RS TRR
Re ad
Reset request
Bus idle response
O n
- c
h i
p b u s
Software reset re quest
Generate rese t
Re set
request flag
PCLK
In debug
state
Power-on rese t
Reset request from OCD tool
Unused (1・b0)
Flash security violation
reset factor
Unus ed
Unus ed
Unus ed
SCRT
Cleared when read
Low vol tage detection( external pow er
sup ply low-voltage detection)
Illegal standby transi tion de tection reset
factor
CPUAR: HW DF
Q
PCLK
S
R
Q
PCLK
In debug
state
Noise
filter
Noise
filter
PCLK
Factor ext end counter
2bit
Generate reset
Re set
request flag
In debug
state
PCLK
Factor ext end counter
2bit
PCLK
Factor ext end counter
2bit
PCLK
Factor ext end counter
2bit
S
R
Q
S
R
Q
S
R
Q
S
R
Q
Generate rese t
Rese t
request flag
In debug
state
Generate rese t
Rese t
request flag
In debug
state
Generate reset
Reset
request flag
In debug
state
S
R
Q
Generate reset
Reset
request flag
In debug
state
S
R
Q
Generate reset
Reset
request flag
PCLK
Factor ext end counter
2bit
PCLK
Factor ext end counter
2bit
Unused (1・b0)
Reset request by simultaneously assert of RSTX and NMIX
RS TX pin
Noise
filter
NMIX pin
Low-voltage detec tion (interna l powe r low-voltage detect ion)
Clock supervisor reset
>
On
-c
hi
p
bus
MB91520 Series
MN705-00010-1v0-E
259