Fujitsu FR81S User Manual
CHAPTER 7: RESET
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
[bit1] PSTF (illegal PLL-run to STandby Flag) : Illegal standby mode transition detection flag
This bit will be set when a watch mode or a stop mode transition has been detected (illegal standby mode
transition) with the PLL clock selected as a clock source. Moreover, the source clock is written automatically
in main mode (CKS=CKM=00). When the PSTRE bit is "1", reset (RST level) is generated.
This bit is cleared by writing "0".
If a read-modify-write instruction is executed, "1" will be read out.
PSTF
Read
Write
0
No illegal standby mode transition has been detected
Clear this bit
1
Illegal standby mode transition has been detected.
No effect
[bit0] HWDF (Hardware WatchDog Flag) : Hardware watchdog detection flag
When a reset factor for the watchdog timer 1 (Hardware watchdog) has been detected, this bit will be set.
This bit is cleared by writing "0".
If a read-modify-write instruction is executed, "1" will be read out.
HWDF
Read
Write
0
No watchdog timer1 (Hardware watchdog) reset factor has
been generated.
Clear this bit
1
Watchdog timer1 (Hardware watchdog) reset factor has been
generated.
No effect
The set factor is given to priority when a set factor and a clear factor are generated at the same time.
Note:
There is a detection flag also in RSTRR:WDG1, and the factor disappears when read once because it is read
clear. Because CPUAR:HWDF is maintained, the factor is maintained until clearing.
MB91520 Series
MN705-00010-1v0-E
265