Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7.2.2.
Reception Interrupts and Flag Setting Timing in Assist Mode ......................................................... 1570
7.2.3.
Reception Interrupts and Flag Setting Timing under using Reception FIFO ................................. 1576
7.2.4.
Transmission Interrupts and Flag Setting Timing .............................................................................. 1577
7.2.5.
Interrupts and Flag Setting Timing under using Transmission FIFO .............................................. 1578
7.2.6.
Timer Interrupts and Flag Setting Timing ........................................................................................... 1579
7.2.7.
Status Interrupts and Flag Setting Timing in Assist Mode ................................................................ 1580
7.3.
Operation of Serial Timer ................................................................................................ 1582
7.4.
Test Mode ........................................................................................................................ 1585
7.4.1.
Manual Mode.......................................................................................................................................... 1586
7.4.2.
Assist Mode ............................................................................................................................................ 1587
7.5.
Operation of LIN Interface (v2.1) ..................................................................................... 1592
7.5.1.
Manual mode.......................................................................................................................................... 1593
7.5.2.
Assist Mode ............................................................................................................................................ 1606
7.5.3.
LIN-UART Baud Rate Selection/Setting ............................................................................................. 1624
7.6.
Setup Procedure and Program Flow ............................................................................... 1625
7.6.1.
Manual mode.......................................................................................................................................... 1626
7.6.2.
Assist mode ............................................................................................................................................ 1630
8.
O
PERATION OF
I
2
C ..................................................................................................................... 1635
8.1.
Interrupts of I
2
C ............................................................................................................... 1636
8.1.1.
List of Interrupts of I
2
C Interface .......................................................................................................... 1636
8.1.2.
Timing of Timer Interrupt Generation and Flag Setting .................................................................... 1638
8.2.
Operation for I
2
C Interface Communication .................................................................... 1639
8.2.1.
I
2
C Bus Start Condition ......................................................................................................................... 1639
8.2.2.
I
2
C Bus Stop Condition ......................................................................................................................... 1639
8.2.3.
I
2
C Bus Repeated Start Condition ....................................................................................................... 1639
8.2.4.
I
2
C Bus Error .......................................................................................................................................... 1640
8.2.5.
Serial Timer Operations ........................................................................................................................ 1641
8.2.6.
Baud Rate Generation .......................................................................................................................... 1643
8.3.
I
2
C Master Mode .............................................................................................................. 1645
8.3.1.
Start Condition Generation ................................................................................................................... 1645
8.3.2.
Slave Address Output ........................................................................................................................... 1647
8.3.3.
Acknowledge Reception by Transmitting First Byte ......................................................................... 1649
8.3.4.
Data Transmission by Master .............................................................................................................. 1656
8.3.5.
Data Reception by Master .................................................................................................................... 1669
8.3.6.
Arbitration Lost ....................................................................................................................................... 1675
8.3.7.
Wait of the Master Mode ....................................................................................................................... 1675
8.3.8.
Repetition Start Condition Issue when DMA Mode Enabled (SSR:DMA=1) ................................. 1676
8.4.
I
2
C Slave Mode ................................................................................................................ 1677
8.4.1.
Detection of Slave Address Matching ................................................................................................. 1678
8.4.2.
Data Direction Bit ................................................................................................................................... 1679
8.4.3.
Slave Mode Reception .......................................................................................................................... 1679
8.4.4.
Slave Mode Transmission .................................................................................................................... 1686
8.5.
Example of I
2
C Flowchart ................................................................................................ 1687
CHAPTER 41: CAN .......................................................................................................................... 1695
1.
O
VERVIEW
................................................................................................................................ 1696
2.
F
EATURES
................................................................................................................................. 1697
3.
C
ONFIGURATION
........................................................................................................................ 1698
4.
R
EGISTERS
............................................................................................................................... 1699
4.1.
Overview .......................................................................................................................... 1700
4.1.1.
List of Base-addresses (Base-addr), External Pins and Buffer Size .............................................. 1701
4.1.2.
List of Overall Control Register ............................................................................................................ 1702
4.1.3.
List of Message Interface Register...................................................................................................... 1703
4.1.4.
List of Message Handler Register ....................................................................................................... 1706
4.2.
Overall Control Registers ................................................................................................ 1708
4.2.1.
CAN Control Register : CTRLR ........................................................................................................... 1709
4.2.2.
CAN Status Register : STATR .............................................................................................................. 1712
4.2.3.
CAN Error Counter : ERRCNT ............................................................................................................ 1715
4.2.4.
CAN Bit Timing Register : BTR ............................................................................................................ 1716
MB91520 Series
MN705-00010-1v0-E
(29)