Fujitsu FR81S User Manual
CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
5.4.3. Reset (RST)
The reset (RST) is shown.
If a reset factor that is not the initialize reset (INIT) level occurs, only a reset (RST) will be issued.
This reset is used for initializing the entire hardware except some registers (see "5.1.1. Initialize Reset
(INIT)").
While this reset is being issued, all clocks become active.
If the main clock is inactive such as in a stop mode before the reset, it takes the main clock oscillation
stabilization wait time. Since the register of the clock control part will be initialized by a reset, the oscillation
stabilization wait time is the default value of this product (2
15
× main clock cycle).
Table 5-3
Oscillation Stabilization Wait Time
(RST)
Is main clock oscillation
inactive before inputting
a reset?
Main clock oscillation stabilization wait time
No
None
Yes
2
15
×Main clock cycle
The following describes each reset issue sequence after reset factors of this reset have been released.
Figure 5-4 Reset (RST) Sequence
L
INIT
Factor
RST
PCLK × 16 cycles
PCLK × 4 cycles
Additional oscillation stabilization wait time in the
event that main clock oscillation stabilization wait
time is required
Because the clock settings register is initialized by reset, the period of the peripheral clock
(PCLK) is 8 times the period of the main clock (MCLK).
MB91520 Series
MN705-00010-1v0-E
291