Fujitsu FR81S User Manual
CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
40
5.5.1. Reset Cycle
The reset cycle is shown.
After the release of reset factors, the reset request is extended during the 4 × peripheral clock (PCLK) cycle.
After that, a reset cycle will be maintained by the period of peripheral clock (PCLK) × 16 cycles for each reset
level. Thus, the minimum number of issue cycles for each reset is 20 cycles. If it requires the main clock
oscillation stabilization wait time, the cycle will be extended for the time required.
MB91520 Series
MN705-00010-1v0-E
293