Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
[bit31] CE (Channel Enable) : Channel operation enabled
This bit controls the operation of the channels. If the request source is set to "software", writing "1" to this
bit starts a DMA transfer according to the configuration. In this case, the CE bit is automatically cleared
when the transfer according to the transfer request completed. If the request source is other than software,
writing "1" to this bit makes channel operation enabled. After enabling operation, a DMA transfer starts
when the corresponding transfer request is detected. In case of a request other than software, the CE bit will
not be automatically cleared if transfer count reload (DCCRn:TCR) is specified. When transfer count reload
is disabled, the CE bit will be cleared when all transfers are finished. If "0" is written while the operation is
going on regardless of the request source, stop transfer in blocks specified in DCCRn:BLK. When writing
"1" again and detecting a new transfer request, the operation restarts.
CE
Channel operation enabled
0
Disabled (initial value)
1
Enabled
[bit30 to bit27] Reserved
Always write "0" to these bits. The read value is "0".
[bit26] AIE (Abnormal completion Interrupt Enable) : Abnormal completion interrupt enabled
This bit controls the generation of interrupts when setting the prohibited values to the DMA channel control
register (DCCR). The items not allowed to set to registers are listed below.
⋅
Transfer mode
: DCCRn:TM = 10
B
⋅
Transfer source address count
: DCCRn:SAC = 10
B
⋅
Transfer destination address count
: DCCRn:DAC = 10
B
⋅
Transfer size
: DCCRn:TS = 11
B
⋅
Demand transfer mode by software request
: DCCRn:RS = 00
B
and DCCRn:TM = 11
B
As for the interrupt factor, refer to the status register (DCSRn).
AIE
Abnormal completion interrupt enabled
0
Disabled (initial value)
1
Enabled
[bit25] SIE (Stop Interrupt Enable) : Transfer suspend interrupt enabled by transfer stop requests
This bit controls the generation of interrupts when a DMA transfer is suspended by a transfer stop request
from the transfer request source. As for the interrupt factor, refer to the status register (DCSRn).
SIE
Transfer suspend interrupt enabled
0
Disabled (initial value)
1
Enabled
MB91520 Series
MN705-00010-1v0-E
311