Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
3.2.
Sector Configuration Diagram ......................................................................................... 1978
4.
R
EGISTERS
............................................................................................................................... 1979
4.1.
WorkFlash Control Register : DFCTLR (WorkFlash ConTroL Register) ......................... 1980
4.2.
WorkFlash Status Register : DFSTR (WorkFlash STatus Register)................................ 1981
4.3.
Flash Interface Control Register : FLIFCTLR (Flash I/F Control Register) ..................... 1983
5.
O
PERATION
............................................................................................................................... 1984
5.1.
Access Mode Setting ....................................................................................................... 1985
5.1.1.
Configuring CPU-ROM Mode below ................................................................................................... 1986
5.1.2.
Configuring CPU Programming Mode ................................................................................................ 1987
5.2.
Writing Flash Memory by CPU ........................................................................................ 1988
5.3.
Automatic Algorithm ........................................................................................................ 1989
5.3.1.
Command Sequence ............................................................................................................................ 1990
5.3.2.
Automatic Algorithm Execution State .................................................................................................. 1994
5.4.
Reset Command.............................................................................................................. 1998
5.5.
Write Command ............................................................................................................... 1999
5.6.
Chip Erase Command ..................................................................................................... 2002
5.7.
Sector Erase Command .................................................................................................. 2003
5.8.
Sector Erase Suspend Command ................................................................................... 2005
5.9.
Security Function ............................................................................................................. 2006
5.9.1.
Flash Security On/Off Determination When Reset Released ......................................................... 2007
5.9.2.
Flash Security Setting Method ............................................................................................................. 2008
5.9.3.
Unlocking Flash Security ...................................................................................................................... 2009
5.9.4.
Flash Access Restrictions When Security is ON ............................................................................... 2010
5.10.
Notes on Using Flash Memory ..................................................................................... 2011
CHAPTER 47: ON CHIP DEBUGGER : OCD .................................................................................. 2013
1.
O
VERVIEW
................................................................................................................................ 2014
2.
F
EATURES
................................................................................................................................. 2015
3.
C
ONFIGURATION
........................................................................................................................ 2016
3.1.
DEBUG I/F Clock............................................................................................................. 2018
3.1.1.
DEBUG I/F Main Clock : M_MCLK ..................................................................................................... 2019
3.1.2.
DEBUG I/F PLL Clock : M_PCLK ........................................................................................................ 2020
4.
R
EGISTERS
............................................................................................................................... 2021
4.1.
DBG Register .................................................................................................................. 2022
4.1.1.
DSU Control Register : DSUCR .......................................................................................................... 2023
4.2.
User IO Register .............................................................................................................. 2024
4.2.1.
User Event Register : UER .................................................................................................................. 2025
4.2.2.
High-Speed Communication Frequency Register : HSCFR ............................................................ 2026
4.2.3.
Message Buffer : MBR .......................................................................................................................... 2027
5.
O
PERATION
............................................................................................................................... 2028
5.1.
OCDU Operating Mode ................................................................................................... 2029
5.1.1.
Operating Mode ..................................................................................................................................... 2030
5.1.2.
Operating Mode Status Transition ....................................................................................................... 2031
5.2.
Overview of DEBUG I/F .................................................................................................. 2032
5.2.1.
Chip Reset Sequence ........................................................................................................................... 2033
5.2.2.
Security Function ................................................................................................................................... 2035
5.3.
Specification Restrictions at Connection to OCD Tool of This Series ............................. 2036
5.3.1.
Clock Setting .......................................................................................................................................... 2037
5.3.2.
Standby Mode ........................................................................................................................................ 2038
5.3.3.
Clock Reset State Transitions .............................................................................................................. 2039
5.3.4.
Summary of Specification Restrictions ............................................................................................... 2041
5.4.
OCD-DSU ID Code and Mount Type Information on This Series ................................... 2045
CHAPTER 48: WAVEFORM GENERATOR ..................................................................................... 2047
1.
O
VERVIEW
................................................................................................................................ 2048
2.
F
EATURES
................................................................................................................................. 2049
3.
C
ONFIGURATION
........................................................................................................................ 2050
4.
R
EGISTERS
............................................................................................................................... 2052
4.1.
Registers for the Waveform Generator ........................................................................... 2053
MB91520 Series
MN705-00010-1v0-E
(33)