Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
4.4. DMA Transfer Count Register 0 to 15 : DTCR0 to 15:
(DMA Transfer Count Register 0 to 15)
This section explains the bit configuration for DMA transfer count register 0 to 15.
These registers are 16-bit registers to indicate the transfer count for each DMAC channel, which exist
independently for each channel. These registers must be accessed as a 16-bit data.
DTCR0 to 15: Address BASE + 0006
H
(Access: Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DTC[15:8]
Initial value
0
0
0
0
0
0
0
0
Attribute
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTC[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
[bit15 to bit0] DTC (DMA Transfer Count) : DMA transfer count
These registers indicate the number of transfer times. DMAC decreases a transfer count at the end of each
block transfer and stops the transfer when the transfer count becomes "0". If "0" is set for transfer count,
transfer will not be performed. Also, the dedicated reload register is provided. If DCCRn:TCR is "1", the
value is returned to the initial value after data transfer.
MB91520 Series
MN705-00010-1v0-E
318