Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
4.7. DMA Transfer Suppression NMI Flag Register : DNMIR
(DMA-halt by NMI Register)
This section explains the bit configuration for DMA transfer suppression flag register.
This register is 8-bit register to suppress DMA transfer by the user NMI. This register must be accessed as a
8-bit data.
DNMIR: Address 0DF6
H
(Access: Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
NMIH
Reserved
NMIHD
Initial value
0
0
0
0
0
0
0
0
Attribute
R,W
R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
R/W
[bit7] NMIH (NMI Halt) : DMA suppression flag (by NMI factor)
If the NMIHD bit is "0", this flag shows an occurrence of the user NMI request. The "H" level of NMI is
detected, and this bit is set to "1". To restart DMA transfer, set this bit to "0".
Writing "1" to this bit is ignored.
NMIH
DMA suppression flag
0
DMA transfer is not suppressed. (Initial value)
1
The DMA transfer has been stopped by user NMI.
[bit6 to bit1] Reserved
Always write "0" to these bits. The read value is "0".
[bit0] NMIHD (NMI Halt Disable) : DMA suppression control (by NMI factor)
The control bit that stops DMA transfer if a user NMI request is generated.
If an NMI occurs when this bit is "0", the DMAC does not restart a new DMA transfer. During DMA
transfer, the controller stops the current DMA transfer when a block unit transfer has completed.
NMIHD
DMA suppression control
0
Stops the DMA transfer by the user NMI. (initial value)
1
Does not stop the DMA transfer by the user NMI.
MB91520 Series
MN705-00010-1v0-E
321