Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
1.
O
VERVIEW
................................................................................................................................ 2170
2.
F
EATURES
................................................................................................................................. 2171
3.
C
ONFIGURATION
........................................................................................................................ 2172
4.
R
EGISTERS
............................................................................................................................... 2173
4.1.
TPU Unlock Register : TPUUNLOCK .............................................................................. 2174
4.2.
TPU Lock Status Register : TPULST .............................................................................. 2175
4.3.
TPU Access Violation Status Register : TPUVST ........................................................... 2176
4.4.
TPU Configuration Register : TPUCFG........................................................................... 2177
4.5.
TPU Timer Interrupt Request Register : TPUTIR ............................................................ 2179
4.6.
TPU Timer Status Register : TPUTST ............................................................................. 2180
4.7.
TPU Timer Interrupt Enable Register : TPUTIE .............................................................. 2181
4.8.
TPU Module ID Register : TPUTMID .............................................................................. 2182
4.9.
TPU Timer Control Register 00 to 07 : TPUTCN00 to 07 ............................................... 2183
4.10.
TPU Timer Control Register 10 to 17 : TPUTCN10 to 17 ............................................ 2185
4.11.
TPU Timer Current Count Register 0 to 7 : TPUTCC0 to 7 ......................................... 2187
5.
O
PERATION
............................................................................................................................... 2188
5.1.
TPU Control Register Access Protection ........................................................................ 2189
5.2.
Global Prescaler .............................................................................................................. 2190
5.3.
Interrupt Control............................................................................................................... 2191
5.4.
Timer Operation ............................................................................................................... 2192
5.5.
Free-run Function ............................................................................................................ 2193
5.6.
Individual Prescaler Function .......................................................................................... 2194
5.7.
Debug Support Function ................................................................................................. 2195
5.8.
Operation Flow ................................................................................................................ 2196
CHAPTER 52: CLOCK MONITOR ................................................................................................... 2197
1.
O
VERVIEW
................................................................................................................................ 2198
2.
F
EATURES
................................................................................................................................. 2199
3.
C
ONFIGURATION
........................................................................................................................ 2200
4.
R
EGISTERS
............................................................................................................................... 2201
4.1.
Clock Monitor Configuration Registers : CMCFG ........................................................... 2201
5.
O
PERATION
D
ESCRIPTION
.......................................................................................................... 2203
6.
S
ETUP
...................................................................................................................................... 2204
7.
Q&A ......................................................................................................................................... 2205
7.1.
How Do I Configure the Output Pin (MONCLK)? ............................................................ 2206
7.2.
How Do I Select the Output Frequency? ......................................................................... 2207
7.3.
How Do I Enable or Disable Clock Monitor Output? ....................................................... 2208
7.4.
How Do I Set the Clock Output Mark Level? ................................................................... 2209
8.
N
OTES
...................................................................................................................................... 2210
APPENDIX ........................................................................................................................................ 2211
A.
I/O
M
AP
.................................................................................................................................... 2212
B.
L
IST OF
I
NTERRUPT
V
ECTOR
...................................................................................................... 2272
C.
P
INS
S
TATUSES IN
S
TATE OF
CPU .............................................................................................. 2296
MB91520 Series
MN705-00010-1v0-E
(35)