Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
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Block Transfer Mode
1-time transfer request causes the 1 block transfer. When a transfer request is detected after the block
transfer, the next 1-block transfer occurs. These operations are repeated until the end of data transfer.
During 1-block data transfer, the data having the size specified by the DCCRn:TS bit is transferred for the
number of times being set by the block size.
Figure 5-2 Each Transfer Mode (Block Transfer)
Start
Set DMACR, DNMIR, DILVR,
DSAR, DDAR, DCSR, DTCR,
DCCR
DSAR, DDAR, DCSR, DTCR,
DCCR
Transfer request?
Transfer request wait
NO
YES
Priority?
Priority wait
NO
YES
NO
Transfer source access
Transfer destination access
NO
BLK count?
Transfer end
DTC count?
YES
YES
MB91520 Series
MN705-00010-1v0-E
332