Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
Transfer request
The transfer request has a request by software or a request by interrupt. The following explains the
relationship between the transfer request detection conditions and the transfer mode.
•
Request by software
If the DCCRn:CE bit is set to "1", a transfer request is detected. When the DMA operation is enabled
(DMACR:DME=1), the priority is determined and the data transfer is started immediately. When the data
transfer by the transfer request has terminated, the DCCRn:CE bit is cleared automatically.
•
Request by interrupt
If the channel operation is enabled (DCCRn:CE=1), a transfer request is awaited. If a peripheral interrupt,
being set by the interrupt controller, has occurred, its transfer request is detected. When the DMA
operation is enabled (DMACR:DME=1), the priority is determined and the data transfer is started
immediately.
When a transfer stop request is asserted from the peripheral, a transfer request is not detected.
Also, an interrupt vector to be used for transfer request must be set for each channel. See the section
"CHAPTER: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS".
* : As the interrupt request from peripherals is detected by an edge, the transfer request cannot be
detected even if the CE bit is reset from "0" to "1" while the interrupt request is enabled. The interrupt
of the peripheral function should be enabled after the CE bit is set to "1".
MB91520 Series
MN705-00010-1v0-E
334